1. Field of the Invention
The present invention relates to MOSFET devices and particularly to MOSFET devices used as low on-impedance switches.
2. Background Information
MOSFET switches are found in many applications and have become common in high frequency, pass-gate switch applications. As technology progressed, such transistor switches became smaller, faster and more power efficient. Often these low on-impedance switches are used to transfer logic data between systems using different power sources, say a 5V system sending and/or receiving logic signals from a 3V system. Typically the power sources determine the high logic levels. Such switches may couple logic systems powered from 5V, 3.3V and/or 1.8V to each other.
Operation at the lower power supply levels, however, encounters issues with respect to threshold requirements inherent in MOSFET transistors. For example, in systems with differing power sources, trouble might be encountered where a logic signal sent from a system is higher than the power supply of the receiving system. Over/under-voltage effects are known to cause catastrophic MOSFET failures.
Known approaches that protect pass-gate switch transistors from over/under-voltages come at a price. For example, using two FETs in series will increase channel resistance, or use increased chip area if the FETs are made larger to reduce channel resistance. Other approaches, as in the above referenced patent application, may not provide full over/under-voltage protection during power up and/or power down operations.
Another approach to over/under-voltage protection is discussed in U.S. Pat. No. 6,163,199 ('199), entitled: “Overvoltage/Undervoltage Tolerant Transfer Gate.” The '199 patent is owned in common with the present application and patent is hereby incorporated herein by reference. The '199 patent provides a more detailed discussion of the limitations of the prior art along with an advance using parallel transistors arranged for over under/under-voltage protection by driving the back gates (bulk contacts) of the transfer transistors involved.
Other known designs focus on lowering insertion loss and increasing the band-width by minimizing the “body effect” that is inherent in MOSFET structures. Insertion loss can be described, generally, as the loss of signal power delivered to a load due to the addition of a less than perfect switch compared to that if the switch were perfect.
A representative prior art design focused on reducing the body effect and insertion loss is found in U.S. Pat. No. 5,818,099 ('099) to Burghartz. The '099 patent describes an n-type MOSFET structure with a p-well that is isolated from the p-type substrate using an n-type well as shown in FIG. 6A of the '099 patent. The '099 low insertion loss circuit embodiment, however, may have larger leakage when there is a signal voltage present and the supply voltage to the transfer switch is turned off, e.g., when power is turned off first to the transfer switch before it is turned off at the sending or receiving systems. Moreover, the switch may become turned on when it should be off during power down.
For example, in FIG. 1 of the '099, a p-type MOSFET is shown with typical biasing of the well to +V. This ensures that the drain/source to well pn junction diode does not become forward biased. However, if the +V supply is at ground (by the supply being turned off) while there is a high logic level, say +5V, at terminal A, the pn drain-well diode in the MOSFET switch is forward biased creating a potentially harmful current path that charges the output capacitor of the +V supply. So the well of the p-type MOSFET will be charged and, thus, the switch is powered when it should be unpowered.
Well current to the Vdd power supply rail may be termed well leakage and remains an issue in some prior art circuits. One bias condition exists where the potential differences among the drain, source and Vdd may be too small for known circuitry to correctly resolve. The present invention addresses this prior art limitation as well as others.
There remain, in prior art MOSFET pass-gate switches, limitations in providing over-voltage tolerance and protection for all values of supply power (Vdd) as may be encountered during normal operations and/or during power up and power down operations. Prior art circuits are especially vulnerable during power up operations, where, for example, an off pass-gate may not remain off during such operations and where excessive leakage currents may occur.
The present invention is directed, inter alia, towards these limitations.